The present invention relates generally to digital circuits, and, more particularly, to a level shifter circuit.
Level shifters are used in integrated circuits that require level shifting voltages of signals that cross one or more circuit domains that operate at different voltage levels. Level shifters are commonly used in a phase-locked loop (PLL) to level shift the PLL output. A PLL includes a voltage-controlled oscillator (VCO) that generates an oscillating signal whose frequency is controlled by an input control voltage. The VCO includes a voltage-to-current converter and a current-controlled oscillator (CCO). The voltage-to-current converter converts the control voltage to a current input and the CCO generates the oscillating signal based on the current input.
A ring oscillator is the most commonly used CCO and has an odd number of cascade-connected inverters, for example, three cascade-connected inverters. Such a ring oscillator generates three oscillating signals that have a 120° phase difference. Each oscillating signal oscillates from zero to a voltage level equal to a top-node voltage of the VCO but less than a supply voltage Vdd of the ring oscillator. A level shifter circuit is connected to the output of the VCO to level shift the voltage level of the oscillating signal to the supply voltage Vdd to obtain a rail-to-rail output voltage.
FIG. 1A shows a schematic circuit diagram of a conventional system 100 that includes a ring oscillator 102 and a level shifter circuit 104. A current source 106, connected to a supply voltage Vdd, supplies an input current to the ring oscillator 102. The ring oscillator 102 includes first through third inverters N1-N3, each connected to a capacitor (not shown). The first through third inverters N1-N3 generate first through third oscillating signals PH1-PH3, each having a voltage level that is equal to a top-node voltage of the ring oscillator 102 and less than the supply voltage Vdd. The three oscillating signals PH1-PH3 further have phase differences of 120°.
The level shifter circuit 104 includes first through fourth transistors 108-114. Source terminals of the first and fourth transistors 108 and 114 are connected to ground. A drain terminal of the first transistor 108 is connected to a drain terminal of the second transistor 110. A gate terminal of the first transistor 108 receives the second oscillating signal PH2. A gate terminal of the second transistor 110 is connected to its drain terminal and a gate terminal of the third transistor 112. Source terminals of the second and third transistors 110 and 112 are connected to the supply voltage Vdd. A drain terminal of the third transistor 112 is connected to a drain terminal of the fourth transistor 114. A gate terminal of the fourth transistor 114 receives the first oscillating signal PH1. A level shifted output is obtained at the drain terminal of the fourth transistor 114. An inverter buffer 116 is connected to the drain terminal of the fourth transistor 114 to buffer the level shifted output.
FIG. 1B is a timing diagram illustrating the oscillating signals PH1-PH3. In operation, when the first oscillating signal PH1 is at low and the second oscillating signal PH2 is high (during time periods t4 to t6 of FIG. 1B), the fourth transistor 114 is switched off and the first transistor 108 is switched on. A drain current flows from the drain terminal to the source terminal of the first transistor 108, pulling down the voltage at its drain terminal to low and switching on the second transistor 110. A drain current flows from the source terminal to the drain terminal of the second transistor 110. The second and third transistors 110 and 112 form a current mirror causing the drain current to be mirrored to the third transistor 112. An output signal is obtained at the drain terminal of the third transistor 112 that is at a voltage level equal to the supply voltage Vdd. Thus, the input to the level shifter circuit 104 is level shifted from the top-node voltage to the supply voltage Vdd (from t4 to t6 of FIG. 1B), i.e., when the oscillating signals PH1 and PH2 are complementary. The operation is similar when the first oscillating signal PH1 is high and the second oscillating signal PH2 is low.
However, from time t0 to t1, the first and second oscillating signals PH1 and PH2 both are high and from time t3 to t4, both the first and second oscillating signals PH1 and PH2 are low, as shown in FIG. 1B. When the level shifter circuit 104 does not receive complementary inputs, it does not provide rail-to-rail output, i.e., it fails to shift the voltage level to Vdd. Such a distorted output hampers the duty cycle of the level shifter circuit 104 output signal.
Therefore, it would be advantageous to have a level shifter circuit that maintains the duty cycle of the oscillating signals input to the level shifter circuit, obtains rail-to-rail output voltage, and improves performance of the conventional level shifter circuit.